Non-volatile Flash memory systems are widely used in modern digital computing devices, such as mobile phones, digital cameras, digital camcorders, computers, and many other digital computing devices. Flash memory systems utilize floating gate transistor memory cells. FIG. 1 shows a typical floating gate memory cell 100 that would be found in many Flash memory systems. The memory cell 100 includes a first source/drain region 105 and a second source/drain region 107. The source/drain regions 105/107 are n+ doped regions formed within a p+ well 111 within a substrate 113. A floating gate 109 and contacted gate 101 are formed between the source/drain regions 105/107. The floating gate 109 is encapsulated in an insulating material 115, such as an oxide, e.g., SiO2. The contacted gate 101 is positioned above and close to, but separated from the floating gate 109. The contacted gate 101 is connected to a conductor 103 of a circuit net.
The floating gate 109 functions as an electron trap to hold a charge present thereon. When the memory cell 100 is programmed, electrons are injected into the floating gate 109. When the memory cell 100 is erased, electrons are removed from the floating gate 109. A change in the number of electrons present in the floating gate 109 causes a change in the threshold voltage VTH of the memory cell 100. When a fixed voltage is applied to the source/drain regions 105/107 of the memory cell 100, a read voltage can be applied to the contacted gate 101 to determine whether or not the memory cell 100 turns on, depending on the threshold voltage VTH of the memory cell 100, which in turn depends on the programmed status of the floating gate 109. If the read voltage applied to the contacted gate 101 is equal to or greater than the existing threshold voltage VTH, the memory cell will turn on, thereby indicating a stored/programmed digital state of “1.” If the read voltage applied to the contacted gate 101 is less than the existing threshold voltage VTH, the memory cell will turn not on, thereby indicating a stored/programmed digital state of “0.”
Over the functional lifetime of the memory cell 100, the ability of the floating gate 109 to retain a programmed charge diminishes. For example, the charge retention ability of the floating gate 109 may diminish as the number of program/erase cycles increases during use of the memory cell 100. The charge retention by the floating gate 109 directly affects the programmed threshold voltage VTH of the memory cell 100. Therefore, over the functional lifetime of the memory cell 100 it is necessary to manage the variation in its charge retention capability in order to ensure the integrity of data read from the memory cell 100. It is within this context that the present invention arises.